1. Field of the Invention
The present invention relates to a Digital-Analog (D/A) Converter, a data driver and a flat panel display using the D/A converter and data driver, and more particularly, the present invention relates to a D/A converter, a data driver and a flat panel display using the D/A converter and data driver capable of minimizing a needed area.
2. Description of the Related Art
Recently, various flat plate displays capable of reducing weight and volume that are disadvantages of cathode ray tubes (CRTs) have been developed. Flat panel displays include Liquid Crystal Displays (LCDs), Field Emission Displays (FEDs), Plasma Display Panels (PDPs), and Organic Light Emitting Displays (OLEDs).
Among the flat panel displays, an LCD expresses an image while controlling a penetration or a non-penetration of light generated by an external back light. Due to a development of a technique, such an LCD may express images of a large area with a high resolution and accordingly, has been used in various fields. Furthermore, an OLED displays images using an organic light emitting diode, which generates light by a recombination of electrons and holes. Since the OLED has a high response speed and has a low power consumption, it comes into the spotlight as the next generation display.
Each LCD and OLED includes pixels, a data driver, and a scan driver. The pixels are disposed at intersection points of the scan lines and the data lines. The data driver drives the data lines. The scan driver drives the scan lines.
The scan driver sequentially supplies a scan signal to the scan lines to sequentially select the pixels in horizontal lines. The data driver supplies a data signal to the data lines in synchronism with the scan signal from the scan lines. Accordingly, the data signal is supplied to pixels selected by the scan signal, and images of a predetermined luminance are expressed corresponding to the supplied data signal.
The data driver uses a D/A converter to convert external digital data into a predetermined voltage value, namely, the data signal.
FIG. 1 is a view of an 8 bit D/A converter.
With reference to FIG. 1, the D/A converter includes a voltage generator 2 and a voltage selector 4. The voltage generator 2 generates voltages. The voltage selector 4 selects any one of the voltages generated by the voltage generator.
The voltage generator 2 divides externally input voltages VRH and VRL into a plurality of voltages. To do this, the voltage generator 2 includes a plurality of resistors R0 to R255, which are disposed between a first voltage VRH and a second voltage VRL. The resistors R0 to R255 are disposed between the first voltage VRH and the second voltage VRL in series, and divide the first voltage VRH and the second voltage VRL into a plurality of voltages.
The voltage selector 4 includes a plurality of switches SW and a decoder 6. The plurality of switches SW are disposed between respective resistors R0 to R255 and an output terminal OUT. The decoder 6 controls a turning-on/off of the plurality of switches SW.
The plurality of switches SW are disposed between respective nodes of the resistors R0 to R255 and an output terminal OUT. For example, when data has eight bits, eight switches are disposed between respective nodes of the resistors R0 to R255 and an output terminal OUT.
The decoder 6 controls turning-on/off of the switches SW according to a bit value of externally input data. In practice, the decoder 6 controls turning-on/off of the switches SW so that one of voltages supplied to the respective resistors R0 to R255 is supplied to an output terminal OUT.
The decoder 6 receives externally supplied data and controls turning-on/off of the switches SW according to a bit value of the data to supply one of voltages generated by the voltage generator 2 to the output terminal OUT. The voltage supplied to the output terminal OUT is supplied to a pixel as a data signal.
However, since the D/A converter includes a plurality of switches SW, a large amount of area is needed. For example, when the data has eight bits, 2048 switches SW are inserted in the voltage selector 4. In particular, because the D/A converter of FIG. 1 is installed at respective data lines or channels, its manufacturing cost is increased due to the D/A converter and the size of a needed panel is increased.